IEEE Std 802.3cq pdf free download

IEEE Std 802.3cq pdf free download.Ethernet Amendment 6: Maintenance #13: Power over Ethernet over 2 pairs.
The PD inrush time duration is defined as beginning with the application of input voltage at the PI when VpD. crosses the PD power supply turn on voltage, Von as defined in Table 33- 18. and ends after Tdelay The inrush current is the initial current drawn by the PD、which is used to charge Cport A PD may limit the inrush curent below Inrush PD to allow for large values of Cporte The PSE either uses the legacy power up method, whereby it limits the inrush current to Inrush until the PD input voltage reaches 99% of steady state. or it limits the inrush current for a fixed amount of time, Tnushe as defined in Table 33- 11. See legacy powerup in 33.2.4.4. PDs shall draw less than Inrush PD. from Inrush min until Tdelay. when connected to a source that meets the requirements of 33.2.7.5. This delay is required so that the PD does not enter a high power state before the PSE has had time to change the available current from the POWER UP to the POWER ON limits. A PD can meet this requirement by either having CPort: charged within TInrush min or by limiting the input inrush current.
PDs with pse power type set to 1 shall conform to PClass PD. and Peak PD requirements within TInrush min as defined in Table 33- 11. PDs with pse_ power type set to 2 shall not exceed Class 3 Ppeak pD- as defined in Table 33-18. from Innsh min until Tdelay 33.3.7.4 Peak operating power Change the second paragraph of 33.3.7.4 as follows: At any static voltage at the PI, and any PD operating condition, the peak power shall not exceed PClass pD max for more than TCUT min, as defined in Table 33- -11 and 5% duty cycle. Peak operating power shall not exceedPpeak PPeak PD max.
When any voltage in the range of0 V to Vport pD. max is applied across the PI at either polarity specified on the conductors for Mode A according to Table 33- -13. the voltage measured across the PI for Mode B with a 100 kQ load resistor connected across Mode B shall not exceed Vbfd- max as specified in Table 33 -18. When any voltage in the range of0 V to Vport pD max is applied across the PI at either polarity specified on the conductors for Mode B according to Table 33- 13. the voltage measured across the PI for Mode A with a 100 k9 load resistor connected across Mode A shall not exceed Vbfd max as specified in Table 33- -18. 33.5 Management function requirements Insert the following as new first paragraph in 33.5: NOTE- 33.5 has been deprecated. Since May 2019, maintenance changes are no longer being considered for this subclause.
33.5.1.2.8 Overload (12.8) Change 33.5.1.2.8 as follows: When read as a one, bit 12.8 indicates that an overload condition has been detected. This bit shall be set to one when the PSE state diagram (Figure 33- -9) enters the state- “ERROR- DELAY OVER’ ERROR DELAY’ due to the ovld detected variable being TRUE. The Overload bit shall be implemented with latching high behavior as defined in 33.5.1.IEEE Std 802.3cq pdf download.