IEEE Std 1838 pdf free download

IEEE Std 1838 pdf free download.Test Access Architecture for Three -Dimensional Stacked Integrated Circuits.
1.2 Three-dimensional integrated circuits (ICs) stacking technology
The market continues to pull for integrated circuits (ICs) with higher performance, better energy-efficiency. and lower cost. While conventional transistor scaling runs into increasing technical and financial hurdles, the baton in the race to create attractive new IC products that meet market expectations is gradually being taken over by innovations in multi-die stack-assembly and packaging techniques. Large-array fine-pitch micro-bumps implement dense high-performance low-power inter-die interconnects. Through-silicon vias in combination with wafer thinning provide electrical connections via the back-side of a die’s substrate. enabling stacks of more than two dies. Interposer dies, possibly implemented in a passive technology, offer low-cost high-performance ways to interconnect multiple dies. Packaging costs can be drastically reduced by using cheaper materials and processes and by turning packaging into a wafer-level operation. The I/O-to-pin fan-out functionality of package substrates can be replaced by redistribution metal layers, cost-effectively manufactured at wafer level. And the cost of plastic or ceramic packages can be circumvented by applying epoxy mold compounds at wafer level.
These and other interconnect, assembly, and packaging technology innovations have led to a wide range of multi-die stack architectures, including so-called “2.SD”-stacked ICs (SICs) consisting of multiple active dies stacked side-by-side on a passive silicon interposer base, 3D”-SlCs comprising a tower of stacked active dies, and multi-tower-SICs that consist of multiple towers of stacked active dies side-by-side on a passive silicon interposer.
1.3 Motivation for a 3D-DtT standard
A well-architected DIT access infrastructure is indispensable for achieving a high-quality test. Not only do we need conventional 2D-Dfl’ structures (such as internal scan chains, test data compression circuitry, IEEE Std 1500 wrappers around embedded cores, and/or built-in self-test (BIST) engines) that provide test access within a single die, we also need new approaches for testing stacked systems. Especially once a (partial or complete) vertical stack has been flu-med (i.e.. in mid-bond, post-bond. or final testing phases), we also need novel 3D-DIT structures that provide test access from (and to) the external stack LOs to (and from) the various dies and inter-die interconnects. For example: if a stack consists of three dies and test access from external test equipment is exclusively possible via the stack 1/Os that are concentrated in, say, Die 1. then Die I and I)ie 2 need to cooperate in transporting test stimuli and responses up and down the stack in order to be able to test Die 3.
To enable separation of the test development as well as test execution tbr the various dies in the stack, the 3D-Df[ architecture should enable modular testing. i.e., tests for dies and interconnect layers between adjacent stacked dies can be developed and executed individually. Several ad-hoc 3D-DfT architectures have been proposed, among others based on IEEE Std 1149.1, IEEE Std 1500, and IEEE Std 16X7. These architectures all have their specific strong and weak points. However, these ad-hoc 3D-DfT architectures do not inter-operate together. Hence, there is a need for a per-die 3D-DfT standard, such that if compliant dies (even if designed and developed by different teams or different companies) are brought together in a die stack, a basic minimum of test features should work across the stack. This is exactly the aim of IEEE Std 1838.
1.4 Context
The Standard for Test Access Architecture for Three-Dimensional Stacked ICs is conceptually related to previously developed design-for-test (DIT) standards, in particular IEEE Std 1149.1, IEEE Std 1500, and IEEE Std 1687. The first two standards specify test access architectures for K’s on hoards (IEEE Std 1149.1) and IP cores embedded within an IC (IEEE Std 1500). IEEE Std 1687 describes an access architecture to embedded instruments. These three previously developed standards have influenced and arc referred to in this standard, so a solid understanding of these standards is strongly recommended.IEEE Std 1838 pdf download.