IEEE Std 1804 pdf free download

IEEE Std 1804 pdf free download.Fault Accounting and Coverage Reporting (FACR) for Digital Modules.
fault: The manifestation of a defect in a circuit, which causes an incorrect logic value to appear on a net in a circuit. A stuck-at fault is an example of a fault. The location of a fault will be referred to as Fault-site.
fault detection: The condition when the presence of a stuck-at fault in the circuit causes the logic value measured at an observation point in the circuit to differ from the logic value expected in the fault-free circuit. For example, a fault is detected when a 0 is expected but a 1 was observed (denoted 0/I), as well as 1/0. A fault is possibly detected in the 0/X and I /X cases.
fault detection status: The classification given to a fault in the fault universe based on its fault detection results during test generation or fault simulation. Fault status can be categorized as detected, possibly detected, undetected, ATPG untestable or structurally untestable, with different classes in each. (Refer to Table I) Si’ti:
fault status.
fault equivalence: Two stuck-at faults are equivalent if they have exactly the same test set, i.e., every test which detects one fault also detects the other fault.
fault grading: A procedure that rates testability by relating the number of faults that can in fact be detected with a test vector set under consideration to the total number of conceivable faults.
fault list: A list of faults for a circuit, one per line, containing three fields (in some defined order with some defined delimiters): the name of the fault-site, the polarity of the fault, and the detection status of the fault. The two examples included in this standard are:
– Fault-site (with full hierarchy) <comma or spaces> Fault Polarity (0 or 1) <comma or spaces> Fault Status (Fault Category as enumerated in Table I)
Fault Polarity (0 or 1) <comma or spaces> Fault Status (Fault Category as enumerated in Table 1)
<comma or spaces> Fault-site (with full hierarchy)
fault simulation: The process of analyzing test patterns to determine the fault detection status of each fault in
the fault universe.
fault universe: The complete set of all fault locations being considered for fault simulation.
leaf cell: A digital circuit element that is represented by Verilog primitives (IEEE Std 1364 [B 1]) or other elements such as memory model, flip-flop, latch, or user-defined primitive (UDP).2
logic value: The (extended) Boolean value (0 or 1 or X or Z) present on a net in a circuit.
single stuck-at fault model: This fault model assumes the presence of only one stuck-at fault at a time (i.e., the stuck-at fault model in the presence of the single fault assumption).
stuck-at fault: This is a condition where a net at the input or output of a library cell, or a primary input (Pt) or primary output (P0) of a circuit, is permanently fixed at I3oolean value 0 (for stuck-at-0 faults, also noted as sa0) or 1 (for stuck-at- I faults, also noted at sa 1).
test generation: The process of creating test patterns consisting of BooLean values comprising stimulus applied to circuit inputs (primary inputs and scan flip-flop Q-outputs) along with response expected at circuit outputs (primary outputs and scan flip-flop D-inputs) to detect faults.
IEEE Std 1804 pdf download.